Sharing Speculation : A Mechanism for Low-Latency Access to Falsely Shared Data

False sharing of data is an important phenomenon affecting performance in shared memory multiprocessors. False sharing results in unnecessary coherency overhead by causing invalidation of the shared cache line, and increasing the latency of the load accessing the cache line. As microprocessors incorporate increasingly large caches with large cache lines, false sharing will become more common, and unless methods are proposed to alleviate, can reduce the performance of shared memory multiprocessors. In this report, we propose sharing speculation, a mechanism to speculatively load values from cache lines that are falsely shared to reduce the latency of these loads, and later validating the speculation when the coherence permissions are eventually granted. We give a specific example of our proposed mechanism in the context of the Grid Processor, and show how the inherent data speculation mechanisms in the Grid Processor lend themselves to the efficient implementation of sharing speculation.